CPUSPEED is written by David Chee Y. Wong, Johor Bahru, Malaysia. The author
retains copyright to this program. CPUSPEED is free software, and you can
distribute it freely as long as it is accompanied by this readme.txt.
CPUSPEED can be downloaded from VOGONS forum: https://www.vogons.org/


DISCLAIMER
==========
The program is intended for retro gaming use, and is distributed in hope that
it will be useful, but WITHOUT ANY WARRANTY, nor the implied warranty of
merchantability or fitness of use. The author assumes no responsibility for
any loss of data or damage to your hardware through the use of this software.
By using this software you agree to these terms. Use at your own risk!


DESCRIPTION
===========

CPUSPEED (CPUSPD) is a DOS/Win98 protected mode program written for retro
gamers, to slow down the speed of modern PCs to those of DOS era. Unlike TSR
programs which use software delays, CPUSPEED reprograms the system hardware
directly and does not stay resident in the system memory. Thus it does not
consume any DOS memory after execution, and the settings will remain effective
until the next reset/reboot.

CPUSPEED controls these three functions of the hardware:

1. CPU cache - turning on/off the CPU L1 & L2 cache. This feature will work
   for all CPUs with on-chip cache, starting from Intel Pentium/AMD K5 and
   including slot 1 CPUs. Since the slow down effect of disabling L2 cache is
   rather small compare to L1 cache, CPUSPEED does not distinguish between
   the two, and will enable or disable them together.

   Support summary: All CPUs with on-chip cache, starting from Intel Pentium &
                    AMD K5 onwards

2. CPU multiplier - for CPUs that support Intel SpeedStep (IST/EIST) or AMD
   PowerNow!/Cool'n'Quiet, CPUSPEED is able to control it's multiplier. AMD
   introduced PowerNow! in their mobile CPUs starting from K6-II+/III+, and
   called it "Cool'n'Quiet" for desktop CPUs starting from Athlon XP. Intel
   started introducing SpeedStep from Pentium 4 630. While AMD's PowerNow!/
   Cool'n'Quiet is well documented and the technical documents are easily
   available, Intel's SpeedStep's documents are sketchy and hard to come by.
   Hence CPUSPEED's SpeedStep implementation is based on guess works and
   experimental results done by various people on the internet, and it is
   likely to have instances where it won't work correctly. With that said,
   the program will try it's best to assist the user to set the value within
   limits when those information are available (mostly via info embedded in
   BIOS).

   Support summary: Intel Pentium 4 630 & AMD mobile K6-II+/III+ & AMD Athlon
                    XP onwards.

3. CPU throttling - this function is available to all systems that support
   ACPI. Throttling of the CPU is achieved by controlling the duty cycle of
   the external CPU clock, which in plain words means turning the clock on
   and off at specific intervals, via the south bridge of the system. The
   ACPI specification was first released in Dec 1996 (around the Pentium 2
   era), so systems built after that time will most likely support it. Please
   note that in early system, ACPI could be enabled/disabled via CMOS setup,
   so please check your CMOS setup if the program reports that no ACPI is
   found. Please also note that some programs will over write the ACPI data
   that the BIOS deposited in high memory. One such example is the popular
   SpeedSys DOS benchmark program - if ESC is pressed while it is doing memory
   tests, the program will abort without restoring the data (which is restored
   upon completion of the tests), hence corrupting the ACPI data. In this case
   simply reboot the system to restore the ACPI data.

   Support summary: All PCs that supports ACPI (made after Dec 1996).

Extra function for Intel Pentium 4 and later CPUs:

4. CPU ODCM (On Demand Clock Modulation) - this function uses the clock
   modulation hardware to control the duty cycle of the internal CPU clock.
   It works independently from south bridge clock throttling, but using the
   same method of skipping clock pulses. For example, if it is set to 1/8,
   it will skip 7 clock pulses before asserting 1 clock, effectively slowing
   down the CPU clock frequency to 1/8. Intel extended the resolution to 1/16
   for later CPUs.

Extra functions for lagacy CPUs:

5. CPU features control:
   Independent L1 cache control - Pentium, Pentium MMX, K6, K6-2, K6-3, K6-2+
                                  & K6-3+.
   L2 cache control - Pentium M, Atom, Dual Core, Core, Core 2, K6-3, K6-2+,
                      K63+, C3 Sameul 2, C3 Ezra & Ezra-T, C3 Nehemiah,
                      Esther A & D.
   Branch prediction - Pentium, Pentium MMX, Winchip 2, 2A, 2B, 3, C3 Sameul 2,
                       C3 Ezra & Ezra-T, C3 Nehemiah.
   Data prefetch - K6-2, K6-3, K6-2+, K6-3+.
   I (code) cache - Pentium MMX, Winchip C6, 2, 2A, 2B, 3, C3 Sameul 2,
                    C3 Ezra & Ezra-T, C3 Nehemiah.
   D (data) cache - Pentium MMX, Winchip C6, 2, 2A, 2B, 3, C3 Sameul 2,
                    C3 Ezra & Ezra-T, C3 Nehemiah.

Extra function for modern AMD CPUs which support p-states:

6. CPU P-states - similar to the multiplier and voltage control of legacy CPUs,
                  except these functions are now moved under p-states (power
                  states of the CPU). Each p-state is pre configured with a set
                  of multiplier value (fid), divisor value (did), and voltage
                  value (vid) by the BIOS during startup, and can be changed
                  by user programs.

Advantage of CPUSPD over older utilities like Throttle and Setmul, and software
solution like slowdown:

CPUSPD uses the same principle as the original Throttle by Jeff Leyda, in that
it uses the south bridge of the PC to slow down the clock frequency supplied
to the CPU, but in addition CPUSPD also allows you to control the CPU cache
and also the multiplier. Furthermore, the original Throttle relies on a
database of chips info stored inside the program, and because it was written
over 16 years ago, many new motherboards with newer south bridges had since
been available which it is unable to control. CPUSPD made use of ACPI instead
to locate the hardware port for throttling the CPU, hence it is universal and
able to throttle all PCs that supports ACPI. The original Throttle is also a
real mode program, so it cannot control the cache when the PC is in VCPI mode
(when EMM386 is running) or protected mode (When Windows 9x is running).

Slowdown is a software solution and a TSR. It stays resident in memory and uses
timer and interrupt to execute software delay loops in the attempt to slow down
the computer. As PCs get faster, longer delay loops are needed which can
quickly exceed the capabilities of the original program, and longer delay loops
couple with timer/interrupts can also interfere with the execution of other
programs (games/applications/etc). Besides that it also takes up precious DOS
memory.

CPUSPD is more like a combination of the Setmul utility by garwin and Throttle,
and expanded for modern hardware. Setmul was originally targeted for VIA C3 and
Cyrix and later expanded for AMD up to K8, but excludes many Intel CPUs (which
it can only control the CPU cache and not multiplier). CPUSPD is able to
control these Intel CPUs as well, including Core 2 CPUs. CPUSPD also offers
throttle control which is absent in Setmul.

Note: some PCI sound cards which use software synthesis might be affected by
CPU slow down. To avoid this issue, use sound cards with hardware emulation
instead. Or better still, use an ISA sound blaster if one is available.

CPUSPEED will attempt to measure the CPU clock speed with the 'i' command.
This is done using Intel's textbook CPU frequency measuring algorithm,
utilizing the TSC (Time Stamp Counter). For newer CPUs which support the
APERF/MPERF (performance) counters, CPUSPEED will also report the PERF speed
measured using these counters. Please note that while TSC is supposedly fixed,
its implementation varies across CPUs/brands, and on some systems it will
vary when the CPU clock is throttled.

CPUSPEED runs in protected mode and requires direct (ring 0) hardware access.
It uses its own DPMI host (CWSDPMI) in pure DOS, and will try to transit to
ring 0 when in Windows 98 DOS box, or when other DOS extender is already
running (e.g. Yamaha YMF744's tsr driver DSDMA uses one and will keep the DOS
extender active.) OSes starting from Windows NT employ a very strict protected
mode, hence CPUSPEED cannot run under these new OSes. CPUSPEED is written in a
combination of assembly (NASM) and C (DJGPP) codes.

Current supported CPUs:
Intel - Pentium, Pentium II, Pentium III, Pentium 4, Pentium D, Dual Core,
        Core Solo/Duo, Core 2, Core ix Gen1-Gen4, Pentium M, Atom CPUs.
AMD - K5, K6, K6-II, K6-III, K6-II+, K6-III+, K7 (Athlon & XP), K8 (Athlon64,
      x2, x3), and K10 (Athlon II, Phenom II, etc) CPUs.
IDT - WinChip C6, 2, 2A, 2B, 3.
VIA - C3 Sameul 2, Ezra, Ezra-T, Nehemiah, Esther A & D.

Please note that not all of these CPUs are tested at this moment (I could only
test on the hardware that I owned). If you encounter a "General Protection
Fault" or "Page Fault", it is most likely due to conditions that the program
doesn't handle.


RUNNING THE PROGRAM
===================

CPUSPD <commands>

where commands are:
 a      - display current cache status, multiplier, throttle, odcm, and
          temperature. (same as commands 'c m t o it').
 c      - cache: display CPU cache status if run without any parameters.
 cd     - disable CPU cache.
 ce     - enable CPU cache.
 c1d    - disable L1 cache.
 c1e    - enable L1 cache.
 c2d    - disable L2 cache.
 c2e    - enable L2 cache.
          Note: Intel family 6 L2 cache can only be enabled/disabled separately
                when L1 cache is enabled. If L1 is disabled, L2 will also be
                disabled.
 ebd    - disable branch prediction.
 ebe    - enable branch prediction.
 edd    - disable data prefetch.
 ede    - enable data prefetch.
 ecd    - disable data cache (D-cache).
 ece    - enable data cache (D-cache).
 eid    - disable instruction cache (I-cache).
 eie    - enable instruction cache (I-cache).
 f      - fid/vid: display fidvid status if run without any parameters.
 fxxyy  - set fid/vid, where xx = fid in hex, and yy = vid in hex.
          please note that the program gives you complete freedom in this
          command; if you choose a fid/vid value unsupported by your CPU,
          or insufficient CPU voltage (vid) for the selected fid, you might
          cause your system to hang up.
          Note: larger fid => bigger multiplier, but larger vid => smaller
                voltage. Please refer to CPU datasheet for further info.
 i      - system information: shows CPU name along with its CPUID.
 ip     - scan and display all PCI devices.
 ipd[xxxx:yyyy] - dump all PCI devices configuration spaces if run without any
          parameters, or dump the device specified by xxxx:yyyy, where xxxx
          is the vendor id and yyyy is the device id.
 ipdb   - dump the PCI configuration spaces of ISA/LPC/other bridges.
 it     - show CPU core and package temperatures, if it has built-in digital
          thermal sensor and package thermal sensor.
 ism    - display system information read from SMBIOS. Please note that some
          manufacturers leave some of the fields blank, so if it's blank that
          just means the information wasn't provided.
 m      - multiplier: display multiplier status if run without any parameters.
 mxx    - set multiplier, where xx is a decimal value from 0 to 99.
          please note that any value less than min/greater than max will give
          you the min/max value.
 o[xx]  - display CPU on demand clock modulation (ODCM) if run without any
          parameters, or set ODCM to xx, where xx is 1 to 8 (or 16 depending
          on CPU). Note that 8 (or 16) will disable ODCM.
 p[x]   - display CPU p-state if run without any parameters, or switch current
          p-state to x, where x is 0-7 in decimal.
 pa     - list all CPU p-states
 pm[ffddvv] - set current CPU p-state values to ffddvv, where ffddvv is the
          fid, did and vid values in hex for AMD cpus (must be 6 digits).
 t      - throttle: display throttle status if run without any parameters.
 txx    - set CPU throttle, where xx = throttle value in decimal. Smaller value
          implies more throttle (slower).
          The slowest is 1 (max throttle) and the fastest is 8 or 16 (no
          throttle), depends on your system. Systems with VIA south bridges
          have 4-bit throttle (1-16) and hence provide finer control. Other
          south bridges commonly have 3-bit throttle (1-8).

The commands are executed in sequence from left to right, and you can repeat
the same command. All commands must be separated with a space, and parameters
should follow their respective commands immediately without any space.


EXAMPLES
========

CPUSPD i
  displays the system information.

CPUSPD i c m t
CPUSPD i a
  displays the system information, cache status, multiplier status, and
  throttle status, in that order.

CPUSPD m i m16 i
  displays multiplier status, the system status, sets multiplier to 16, and
  displays system status again.

CPUSPD i s
  displays the system information and SMBIOS information.

CPUSPD i m0 t1 cd i
  displays the system info, sets multiplier to 0, throttle to 1, disable cache,
  displays system info again.

CPUSPD t4 i t1 i
  sets throttle to 4, displays system info, sets throttle to 1, display system
  info again.

ACKNOWLEDGEMENTS
================
Special thanks to the following Vogons forumers for their help in testing the
program:
johnnycontrario, SaxxonPike, JazeFox, Bancho, red-ray.
Special thanks to the following Vogons forumers for their help in suggesting
new features and sharing their knowlege:
Falcosoft, PARUS.

KNOWN ISSUES
============

Not tested under Windows 95 and Windows ME.


REVISION HISTORY
================
1.0     06-02-20    Initial release.
1.1     06-03-20    Resolved incompatibilty issue with Yamaha's DSDMA sound
                    driver.
1.2     06-09-20    Resolved ACPI detecting issue when ACPI table is located
                    within 1MB DOS memory.
                    Added DOS version check under NT.
1.3     06-19-20    Added support for VIA C3 CPUs: Samuel, Samuel 2, Ezra,
                    Ezra-T, and Nehemiah.
1.4     07-08-20    Added L2 cache control for Intel family 6 CPUs: Pentium 3
                    (Katmai, Coppermine, Tualatin), Pentium M, Core, Core 2.
                    Added south bridge database support for throttling, in
                    addition to ACPI. This is to support systems without ACPI
                    implementation in BIOS (e.g. POS, thin clients, etc). The
                    program will first use ACPI to try finding the throttle
                    port. If ACPI is not available, it will then fallback to
                    the databse.
                    Added PCI device scan to help identify the south bridge
                    devices. Note: CPUSPD.SBI file must be in the same folder
                    as CPUSPD.EXE.
1.5     07-11-20    Added on demand clock modulation (ODCM) function for Intel
                    Pentium 4 and later CPUs (Pentium D, Duo Core, Core,
                    Core 2).
2.0     08-09-20    Added VIA Esther support for both multiplier and fidvid
                    control.
                    Added L2 cache, I-cache, D-cache, and branch prediction
                    control for VIA & WinChip CPUs.
                    Added L1 cache, code cache, data cache, and branch
                    prediction control for Intel Pentium & MMX CPUs.
                    Added L1 cache, L2 cache, and data prefetch control for
                    AMD K6 CPUs.
                    Added voltage display for vidfid control.
                    Added CPU core and package temperature display for Intel
                    and VIA Esther/Nano CPUs.
                    Restructured and tidied up some portions of program.
                    Fixed issue with acpi throttling causes GPF on some
                    motherboards.
2.1    15-01-24     Minor bug fixes.
                    Added p-states control for Intel, AMD, and Transmeta
                    Move commands: cdd/cde => edd/ede, cid/cie => eid/eie.
